Changeset 326 for applications/pmsm/simulator_zdenek

Timestamp:

04/25/09 22:22:00 (16 years ago)

Author:

smidl

Message:

pmsm + UI for EKF

Location:

applications/pmsm/simulator_zdenek

Files:

• ekf_example/simul.cpp (modified) (1 diff)
• simulator.cpp (modified) (13 diffs)

applications/pmsm/simulator_zdenek/ekf_example/simul.cpp

@@ -22 +22 @@
 #define CHYBA_POLOHY    (0./180.*M_PI)  // chyba +/-8 stupnu elektrickych pro senzorovany loziskovy stit
 
-#define MODULACE        1       // 0...sinusova PWM, 1...PWM se 3.harmonickou
+#define MODULACE        0       // 0...sinusova PWM, 1...PWM se 3.harmonickou
 #define REZIM_REGULACE  1       // 0...reg. momentu, 1...reg.rychlosti, 2... Isqw=sqrt(Imax^2-Id^2) - max. moment
 

applications/pmsm/simulator_zdenek/simulator.cpp

@@ -7 +7 @@
    Z. Peroutka
 
-Rev. 16.3.2008
+Rev. 25.4.2009
 
 */
@@ -13 +13 @@
 #define _USE_MATH_DEFINES
 
+#include <stdio.h>
 #include <math.h>
 #include <stdlib.h> //na linuxu je abs v stdlib
@@ -77 +78 @@
 static double ualfa=0., ubeta=0.;
 
+// PWM - improvement of dead-time effect emulation
+static unsigned int start_pwm=1;
+static int uact[3]={1,1,1};
+static int ureq[3]={1,1,1};
+static unsigned int DT_counter[3]={0,0,0};
+static unsigned int DT_counter_mez;
+
+// debug
+static double debug_pwm;
+FILE *fdebug;
 
 /////////////////// POMOCNE FUNKCE //////////////////////////////////
@@ -137 +148 @@
   citac2=abs(0-(int)(DT/h)); //VS: oprava, je to spravne?
   citac_PR=h_reg_counter_mez;
+  DT_counter_mez = (int)(DT/h);
 
   // first interrupt occur after first period match => add 1 to both counter registers
@@ -142 +154 @@
   citac2--;
 
-  modulace=1;           // THIPWM
+  modulace=0;           // THIPWM
   if (modulace==1)
     U_modulace=Ucn/sqrt(3.);
@@ -154 +166 @@
 
   init_regulace(Ls,Fmag,kp,p,h_reg_real);
+  
+  // !!d!!
+//  fdebug=fopen("data_debug.txt","w");
 }
 
@@ -172 +187 @@
   // emulation of carrier - timer
   up=((double)citac/citac_PR-0.5)*Ucn;
-  up2=((double)citac2/citac_PR-0.5)*Ucn;
-
+    
   iabc[0]=*x;
   iabc[1]=(-*x+sqrt(3.)**(x+1))/2.;
@@ -196 +210 @@
     dd[i]=dtr[i]*.73;
   }
-
-  // implementation of voltage drops and dead-times
+  
+  // mitigation of the voltage drops
+/* for (i=0;i<3;i++)
+ {
+   dtr[i]=0.;
+   dd[i]=0.;
+ }
+/**/ 
+ 
+ // PWM compare emulation
   for (i=0;i<3;i++)
-    if (iabc[i]>=0)
-      if ((ur[i]>up) && (ur[i]>up2))
-        ustr[i]=Uc/2-dtr[i];
+          if (ur[i]>up)
+                  ureq[i]=1;
       else
-        ustr[i]=-(Uc/2+dd[i]);
+                  ureq[i]=-1;
+
+  // First entrace into PWM - actual switching combination is initiated with required switching state
+  if (start_pwm == 1)
+  {       
+          for (i=0;i<3;i++)
+                  uact[i]=ureq[i];
+          start_pwm=0;
+  }
+  
+  // Dead-time effect has no impact on switching combination, when switching from transistor to diode
+  for (i=0;i<3;i++)
+  {
+          if ((iabc[i]>0.5) && (uact[i]==1))
+            uact[i]=ureq[i];
+                  
+          if ((iabc[i]<-0.5) && (uact[i]==-1))
+            uact[i]=ureq[i];
+  }
+/**/
+    
+/*  for (i=0;i<3;i++)
+          uact[i]=ureq[i];*/
+  
+  // Dead-time effect emulation
+  for (i=0;i<3;i++)
+    if ((uact[i]!=ureq[i]) && (DT_counter[i]<DT_counter_mez))
+      DT_counter[i]++;
     else
-      if ((ur[i]<up) && (ur[i]<up2))
-        ustr[i]=-(Uc/2-dtr[i]);
-      else
-        ustr[i]=Uc/2+dd[i];
-
-// phase voltages
+        {
+          uact[i]=ureq[i];
+          DT_counter[i]=0;
+        }
+        
+        // inverter phase voltage computation
+        for (i=0;i<3;i++)
+                ustr[i]=uact[i]*Uc/2.;
+        
+        // implementation of voltage drops
+        for (i=0;i<3;i++)
+          if (iabc[i]>0)
+                if (uact[i]==1)
+                  ustr[i]-=dtr[i];
+            else
+                  ustr[i]-=dd[i];
+          else
+                if (uact[i]==-1)
+                  ustr[i]+=dtr[i];
+            else
+                  ustr[i]+=dd[i];
+/**/  
+  // phase voltages
   ua=(2.*ustr[0]-ustr[1]-ustr[2])/3.;
   ub=(2.*ustr[1]-ustr[0]-ustr[2])/3.;
@@ -218 +283 @@
   *us=(2.*ua-ub-uc)/3.;
   *(us+1)=(ub-uc)/sqrt(3.);
+  
+  // sinusoidal inverter!!!!
+//  *us=ur[0];
+//  *(us+1)=(ur[1]-ur[2])/sqrt(3.);
 
   // emulation of DSP timers
@@ -253 +322 @@
   sum_isx_av+=*x;
   sum_isy_av+=*(x+1);
+  
+  debug_pwm = ur[0]; // !!!!
+  // !!d!!
+//  fprintf(fdebug,"%f %f %f \n",ustr[0],*us,x[0]);
 }
 
@@ -349 +422 @@
 //       ualfa=Umk*cos(*(u+1));
 //       ub=Umk*cos(*(u+1)-2./3.*M_PI);
-      KalmanObs[0]=ualfa;                     // usx
+      KalmanObs[0]=ualfa; //debug_pwm;                     // usx
       //KalmanObs[1]=(ualfa+2.*ub)/sqrt(3.);    // usy
       KalmanObs[1]=ubeta;    // usy
@@ -368 +441 @@
       KalmanObs[9]=isy_av;      
 
-      vektor_regulace(0,0,Urm_max,Ww,u,Isx,Isy,theta,speed,U_modulace,Uc,Ucn,REZIM_REGULACE);   // rezim=1 ... reg. rychlosti, rezim=0 ... reg. momentu
+       vektor_regulace(0,0,Urm_max,Ww,u,Isx,Isy,theta,speed,U_modulace,Uc,Ucn,REZIM_REGULACE);  // rezim=1 ... reg. rychlosti, rezim=0 ... reg. momentu
                                                                                                                 // rezim=2 ... Iqw=sqrt(Imax^2-Idw^2)
-      // emulation of the real sampling of A/D converter
+      
+/*        *u=2*15.0;
+          *(u+1)+=2*0.00157;*/
+// emulation of the real sampling of A/D converter
       Isx=x[0];Isy=x[1];speed=x[2];theta=x[3];
 
       // include ideal commanded stator voltage 
-      Umk=*u*Uc/Ucn;
+      Umk=*u*Uc/Ucn;// !!!!
       ualfa=Umk*cos(*(u+1));               // usx = usa
       ub=Umk*cos(*(u+1)-2./3.*M_PI);
@@ -393 +469 @@
   double kor_Uc;
 
-  *u=sqrt(ua*ua+ub*ub);
-  *(u+1)=uhel(ua,ub);
-
+   *u=sqrt(ua*ua+ub*ub);
+   *(u+1)=uhel(ua,ub);
+  
+/*  *u=5.0;
+  *(u+1)+=0.00157;*/
   // uprava velikosti vzhledem k Uc!=Ucn
   kor_Uc=Ucn/230.;